1. Field of the Invention
The present invention relates to a semiconductor integrated circuit in which a wafer test is performed to check functions of a plurality of input/output ports connected with a plurality of internal circuits.
2. Description of Related Art
FIG. 10 is a diagram showing a positional relationship among an internal circuit area and a plurality of input/output ports arranged around the internal circuit area in a conventional semiconductor integrated circuit. In FIG. 10, 101 indicates a rectangular-shaped semiconductor chip on which a conventional semiconductor integrated circuit is arranged, and 105 indicates a rectangular-shaped internal circuit area arranged in a central portion of the conventional semiconductor integrated circuit. A plurality of internal circuits such as logical circuits and an electric power supply circuit are arranged in the internal circuit area 105. 104 indicates a plurality of input/output (I/O) ports, arranged on the four outer circumferential sides of the rectangular-shaped internal circuit area 105, for respectively inputting external data to the corresponding internal circuit and outputting internal data produced in the corresponding internal circuit to the outside. Each input/output port 104 is composed of a wire-bonding pad (hereinafter, called a pad) 103 and a buffer 102. Each pad 103 is connected with a bonding wire (not shown) in an normal operation to input or output data from/to an external apparatus (not shown) through the bonding wire. 106 indicates a probe. The probe 106 is connected with the pad 103 of each input/output port 104 in a wafer test. In the wafer test, an input test signal, an output test signal, various control signals and a voltage signal are transmitted between the probe 106 and each input/output port 104 to check a function of the corresponding internal circuit connected with the input/output port 104.
An operation of the conventional semiconductor integrated circuit is described.
To check the function of each internal circuit (for example, each logical circuit) arranged in the internal circuit area 105 in the wafer test, the probe 106 is connected with the pad 103 of the input/output port 104 corresponding to the internal circuit, and the wafer test is performed. That is, an input test signal and various control signals supplied from the probe 106 are input to the internal circuit through the pad 103 and the buffer 102 of the input/output port 104, and an output test signal produced in the internal circuit is output to the probe 106 through the input/output port 104. Also, a voltage signal supplied from the probe 106 is input to a specific input/output port 104 used for the electric power supply to supply an electric power to the corresponding internal circuit.
However, because the probe 106 is connected with each of the pads 103 of the input/output ports 104 in the wafer test to check the functions of the internal circuits, there is a case where one pad 103 is damaged in the connection of the probe 106 with the pad 103. In this case, even though a bonding wire is connected with the pad 103 in an normal operation, there is a problem that a contact failure occurs between the bonding wire and the pad 103 because the bonding wire is not electrically connected with the pad 103.
Also, there is another conventional semiconductor integrated circuit in which a for-wafer-test pad exclusively used for the wafer test is additionally arranged for each input/output port 104. In this conventional semiconductor integrated circuit, because a probe is connected with the for-wafer-test pad in the wafer test, the bonding wire can be reliably connected with the pad 103 in the normal operation without any connection failure. However, because a large number of input/output ports 104 are usually arranged in the conventional semiconductor integrated circuit, a large number of for-wafer-test pads are required, so that the size of the conventional semiconductor integrated circuit is considerably increased.
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional semiconductor integrated circuit, a semiconductor integrated circuit in which the occurrence of a contact failure between a bonding wire and a pad is prevented in the connection of the bonding wire with the pad in a normal operation performed after a wafer test while suppressing the increase of the size of the semiconductor integrated circuit having internal circuits.
The object is achieved by the provision of a semiconductor integrated circuit comprising a first for-wafer-test input/output element, exclusively used for a wafer test, for outputting a plurality of test signals to be used in the wafer test; a second for-wafer-test input/output element, exclusively used for the wafer test, for outputting a control signal to be used in the wafer test; a third for-wafer-test input/output element, exclusively used for a wafer test, for receiving the test signals used in the wafer test; and a plurality of input/output ports, which each correspond to an internal circuit and are serially arranged for a flow of the test signals output from the first for-wafer-test input/output element, for receiving the test signals serially output from the first for-wafer-test input/output element, outputting the test signals to the corresponding internal circuits according to the control signal received from the second for-wafer-test input/output element, reading out the test signals from the corresponding internal circuits according to the control signal and serially transferring the test signals to the third for-wafer-test input/output element according to the control signal.
In the above configuration, when the test signals are output to the corresponding internal circuits, a logical calculation or the like is performed for the test signal in each internal circuit to produce the test signal as a result of the logical calculation. Therefore, functions of the internal circuits can be checked in the wafer test by analyzing the test signals read out from the internal circuits. Also, because the test signals and the control signals are sent from the outside to the input/output ports through the first and second for-wafer-test input/output elements and because the test signals processed in the internal circuits are sent from the input/output ports to the outside through the third for-wafer-test input/output element, though a probe is connected with each for-wafer-test input/output element in the wafer test, no probe is connected with each input/output port in the wafer test.
Accordingly, each input/output port is not physically damaged in the wafer test, so that a bonding wire can be connected with each input/output port in a normal operation performed after the wafer test without any contact failure between the bonding wire and each input/output port. Therefore, the yield of the semiconductor integrated circuit can be improved.
Also, because the first, second and third for-wafer-test input/output elements are arranged in a set for all the input/output ports, the increase of the size of the semiconductor integrated circuit can be suppressed as compared with a case where one for-wafer-test input/output element is arranged for each input/output port.
It is preferred that each input/output port comprises a first shift register, the test signals serially output from the first for-wafer-test input/output element are held in the first shift registers of the input/output ports, the test signals held in the first shift registers are output to the corresponding internal circuits according to the control signal received from the second for-wafer-test input/output element, the test signals readout from the corresponding internal circuits according to the control signal are held in the first shift registers, and the test signals held in the first shift registers are transferred to the third for-wafer-test input/output element according to the control signal.
In the above configuration, the test signals are transmitted to the first shift registers, the internal circuits and the first shift registers in that order. therefore, the configuration of each input/output port required for the wafer test can be simplified.
It is also preferred that the semiconductor integrated circuit further comprises a fourth for-wafer-test input/output element for outputting a voltage control signal; and a fifth for-wafer-test input/output element for receiving an output voltage signal, wherein a specific input/output port selected from the input/output ports comprises a pad to which a voltage is applied; and a second shift register for holding the voltage control signal output from the fourth for-wafer-test input/output element in the wafer test according to the control signal received from the second for-wafer-test input/output element to transfer the output voltage signal indicating a value of the voltage applied to the pad to the fifth for-wafer-test input/output element according to the voltage control signal held in the second shift register.
In the above configuration, a voltage is applied to the pad in the wafer test, the voltage control signal output from the fourth for-wafer-test input/output element is held in the second shift register in the wafer test, and the value of the voltage applied to the pad is transferred to the fifth for-wafer-test input/output element according to the voltage control signal. Therefore, the voltage applied to the pad can be detected in the wafer test before the voltage is sent to the corresponding internal circuit in the normal operation.
It is also preferred that a frequency of a particular test signal, which is selected from the test signals and is output to a particular internal circuit corresponding to a particular input/output port selected from the input/output ports, is higher than that of the other test signals output to the internal circuits other than the particular internal circuit, the particular test signal is sent to the particular input/output port separately from the other test signals serially sent from the first for-wafer-test input/output element to the input/output ports other than the particular input/output port, and the particular input/output port comprises
a for-wafer-test pad, exclusively used for a wafer test, for receiving the particular test signal in the wafer test; and
a selector for selecting the particular test signal received by the for-wafer-test pad or an operation signal according to the control signal received from the second for-wafer-test input/output element to output the particular test signal to the particular internal circuit in the wafer test and to output the operation signal to the particular internal circuit in a normal operation.
In the above configuration, in cases where the particular test signal, of which the frequency is higher than that of the other test signals, is required in the particular internal circuit because the frequency of the operation signal to be processed in the particular internal circuit is higher than that of the other test signals, the particular test signal is sent to the for-wafer-test pad of the particular input/output port separately from the other test signals serially sent to the other input/output ports. Thereafter, in case of the wafer test, the particular test signal is selected by the selector and is output to the particular internal circuit. Also, in case of the normal operation, the operation signal is selected by the selector and is output to the particular internal circuit.
Accordingly, because a probe is connected with the for-wafer-test pad in the wafer test, in cases where a bonding wire is connected with the particular input/output port in the normal operation, no connection failure between the particular input/output port and the bonding wire occurs in the normal operation.
Also, because the particular test signal is sent to the particular input/output port separately from the other test signals serially sent to the other input/output ports, it is not required to reset an entire test pattern of the test signals including the particular test signal, so that a time required for the wafer test can be shortened.
It is also preferred that the semiconductor integrated circuit further comprises a fourth for-wafer-test input/output element, exclusively used for the wafer test, for outputting a plurality of second test signals of which the frequency is higher than that of the test signals output from the first for-wafer-test input/output element; a fifth for-wafer-test input/output element, exclusively used for the wafer test, for outputting a second control signal; and a sixth for-wafer-test input/output element, exclusively used for the wafer test, for receiving the second test signals used in the wafer test, wherein the frequency of particular signals, which are required in one or more particular internal circuits selected from the internal circuits, is higher than that of signals required in internal circuits other than the particular internal circuits, the second test signals serially output from the fourth for-wafer-test input/output element are received by one or more particular input/output ports corresponding to the particular internal circuits in place of the test signals serially output from the first for-wafer-test input/output element, the second test signals are output to the particular internal circuits according to the second control signal received from the fifth for-wafer-test input/output element, the second test signals are read out from the particular internal circuits according to the second control signal, and the second test signals are serially transferred to the sixth for-wafer-test input/output element according to the second control signal.
In the above configuration, in cases where the frequency of particular signals required in the particular internal circuits is higher than that of signals required in the other internal circuits, the wafer test of the particular internal circuits is performed, in the same manner as the wafer test of the other internal circuits, by using the set of fourth, fifth and sixth for-wafer-test input/output elements.
Accordingly, even though the frequency of particular signals required in the particular internal circuits is higher than that of signals required in the other internal circuits, because the wafer test of the particular internal circuits can be performed separately from the wafer test of the other internal circuits, a time required for the wafer tests of all the internal circuits can be shortened. Also, the number of test patterns required for the wafer tests of all the internal circuits can be reduced, and a transfer time of the test signals serially sent to the input/output ports other than the particular input/output ports can be shortened as compared with that of the test signals serially sent to all the input/output ports.
It is also preferred that the internal circuits corresponding to the input/output ports are arranged in a central area of the semiconductor integrated circuit, and the first for-wafer-test input/output element and the second for-wafer-test input/output element are arranged on one or more corners of the semiconductor integrated circuit.
The input/output ports are arranged on outer circumferential sides of an internal circuit area, in which the internal circuits are arranged, because each input/output port has an output buffer. In contrast, because each of the first and second for-wafer-test input/output elements has no output buffer, a size of each of the first and second for-wafer-test input/output elements is smaller than those of the input/output ports. Therefore, the first and second for-wafer-test input/output elements can be arranged on one or more corners of the semiconductor integrated circuit.
Accordingly, the size of the semiconductor integrated circuit can be made small.
It is also preferred that a specific input/output port arranged in the final stage among the input/output ports, which are serially arranged for the flow of the test signals serially output from the first for-wafer-test input/output element, has an output buffer required in the third for-wafer-test input/output element while removing the output buffer from the third for-wafer-test input/output element, the internal circuits corresponding to the input/output ports are arranged in a central area of the semiconductor integrated circuit, and the third for-wafer-test input/output element is arranged on a corner of the semiconductor integrated circuit.
Because the output buffer of the third for-wafer-test input/output element is removed and arranged in the specific input/output port arranged in the final stage among the input/output ports, the size of-the third for-wafer-test input/output element is made small on condition that the test signals processed in the internal circuits are smoothly output to the third for-wafer-test input/output element. Therefore, the third for-wafer-test input/output element can be arranged on the corner of the semiconductor integrated circuit, and the size of the semiconductor integrated circuit can be made small.
It is also preferred that the semiconductor integrated circuit further comprises a for-electric-power-supply input/output port for supplying an electric power to the input/output ports, the internal circuits corresponding to the input/output ports are arranged in a central area of the semiconductor integrated circuit, and the for-electric-power-supply input/output port is arranged on a corner of the semiconductor integrated circuit.
Because the for-electric-power-supply input/output port has only a for-electric-power-supply pad, the for-electric-power-supply input/output port can be arranged on one corner of the semiconductor integrated circuit. Therefore, even though the for-electric-power-supply input/output port is added to the semiconductor integrated circuit, the increase of the size of the semiconductor integrated circuit can be suppressed.